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Qinlin Chen (陈钦霖)

• Ph.D. Student.
• Pascal Research Group, Institute of Computer Software.
• School of Computer Science, Nanjing University.

Contact:

• Office: 529, Building of Computer Science and Technology, Xianlin Campus of Nanjing University.
• Email: chenqinlin98 AT gmail DOT com.

About

I am studying for a Ph.D. degree in the Pascal Research Group at Nanjing University. I am supervised by Yue Li (李樾). I have my interest in programming languages, software reliability methods, and infrastructure systems. Currently I am focusing on applying modern PL&SE techniques to hardware descrpition languages.

Education

• Nanjing University (Sep 2022 - now), China
  • Studying for a Ph.D. Degree in Computer Science and Technology
  • Supervisor: Yue Li & Tian Tan
• Nanjing University (Sep 2020 - Jul 2022), China
  • Studying for a M.Sc. Degree in Computer Science and Technology
  • Advisor: Yanyan Jiang
• Nanjing University (Sep 2016 - Jul 2020), China
  • Recevied a B.Sc. Degree in Computer Science and Technology

Publications

Corresponding authors are marked with an asterisk (*).

Hardware Static Analysis

• (PLDI’26) Exploiting Sophisticated Static Analysis for Verilog. [PDF] [Homepage]
  • Qinlin Chen, Nairen Zhang, Jinpeng Wang, Jiacai Cui, Tian Tan*, Xiaoxing Ma, Chang Xu, Jian Lu, and Yue Li*.
  • This is the conference version of Qihe (ArXiv’26).
• (ArXiv’26) Qihe: A General-Purpose Static Analysis Framework for Verilog. [PDF] [Homepage]
  • Qinlin Chen, Nairen Zhang, Jinpeng Wang, Jiacai Cui, Tian Tan*, Xiaoxing Ma, Chang Xu, Jian Lu, and Yue Li*.
• (POPL’26) ChiSA: Static Analysis for Lightweight Chisel Verification. [PDF] [Artifact]
  • Jiacai Cui, Qinlin Chen, Zhongsheng Zhan, Tian Tan*, and Yue Li*.

Hardware Programming Languages and Semantics

• (OOPSLA’23) The Essence of Verilog: A Tractable and Tested Operational Semantics for Verilog. [PDF] [Artifact]
  • Qinlin Chen, Nairen Zhang, Jinpeng Wang, Tian Tan*, Chang Xu, Xiaoxing Ma, and Yue Li*.
  • 🏆 Distinguished Artifact Award

Hardware Acceleration

• (OOPSLA’26) When FPGA Meets Dataflow Analysis: An Explorative Step. [PDF] [Artifact]
  • Fang Wei, Qinlin Chen (co-first author), Nairen Zhang, Jiacai Cui, Tian Tan*, Zhiqiang Zuo, and Yue Li*.

Projects

• Qihe: The First General-Purpose Static Analysis Framework for Verilog
  • Unlike traditional Verilog linters, which are limited to basic code-style or syntactic checks, Qihe enables deep semantic analysis of hardware designs at the RTL stage.
  • Qihe is primarily designed and maintained by me, with significant contributions from Nairen Zhang, Jinpeng Wang, and Jiacai Cui.
• Vide: A Modern SystemVerilog Coding IDE
  • It brings hardware developers 10+ code analysis features often missing from traditional hardware IDEs, such as precise completion, code annotations, automatic refactoring, and semantic highlighting.
  • Vide was initially maintained by Jiayan Wu and is now maintained by Jiarong Hong.

Qihe and Vide are complementary. Vide is optimized for fast, immediate static-analysis feedback during hardware development. This makes it less suited to deeper, more resource-intensive analyses, such as hardware bug detection, which are the focus of Qihe.

Services

• Peer Review
  • Reviewer for TOSEM, 2026
  • Artifact Evaluation Committee Member for OOPSLA, 2024
    • 🏆 Distinguished Artifact Reviewer Award
• Teaching Assistant:
  • Static Program Analysis (Fall 2021), Nanjing University.
  • Structure and Interpretation of Computer Programs (Fall 2020), Nanjing University.

Awards & Honors

• 2025年南京大学博士研究生创优项目
• OOPSLA 2024 Distinguished Artifact Reviewer Award
• OOPSLA 2023 Distinguished Artifact Award
• 2023年江苏银行奖学金 (Bank of Jiangsu Scholarship, 2023)
• 南京大学2020届优秀毕业生 (Outstanding Graduates Awards of Nanjing University, 2020)
• 2019年南京大学拔尖计划奖学金特等奖

Posts

I wrote some posts (in Chinese) on Zhihu for fun. Click here if you have any interests.